SafeNet's security chips optimized for IP security
By Loring Wirbel, EE Times
Sep 15, 2003 (9:16 AM)

COLORADO SPRINGS, Colo. — SafeNet Inc. is adding to its Momentum line of chip sets optimized for Internet Protocol secure applications. The additions include the 1840 and 1842 chips aimed at half-duplex support of OC-12 (622-Mbit) and (OC-48) 2.48-Gbit channels and the full-duplex 1841 chip for special secure processing needs.

SafeNet (Baltimore), a network security technology provider founded 20 years ago by two former National Security Agency engineers, has assembled a suite of system security tools to sell directly to government and financial industries and OEM chips and boards to sell indirectly to enterprise customers. In its two decades, the company has acquired such security pioneers as Cylink Corp., Raqia Networks Inc. and SecureLink Inc., integrating their products into its own security portfolio.

The Momentum chip line is just one facet of a broader program for OEMs and semiconductor partners. The company is licensing much of its encryption and virtual private network intellectual property cores directly to OEMs and chip-set suppliers. Next year, it plans to offer a highly secure, high-performance system-on-chip-the result of direct collaboration with U.S. intelligence and communication agencies.

The company's SafeXcel-184x family addresses a need for better IPsec performance in VPN applications, said vice president of sales Prakash Panjwani. The Momentum series scales down to low-end applications in residential and corporate gateways, while offering independently optimized packet and crypto engines that can fine-tune power dissipation for maximizing IPsec performance while dissipating a few watts.

Private and public


The chips can accelerate both private-key FIPS algorithms, such as Data Encryption Standard, Triple-DES and Advanced Encryption Standard; as well as public-key algorithms, such as RSA and Diffie-Hellman. SafeNet has designed the Momentum line to segment control-plane and data-plane interfaces, emphasizing PCI-X for control interfaces and SPI-3 (in the 1841 and 1842 chips) for independent high-speed I/O in the datapath.

The IPsec packet throughput of the family ranges from 550 Mbits/second to 3.3 Gbits/s. The number of 1,024-bit RSA signatures that can be handled per second ranges from 700 to 2,100. The chip set is one of the first to implement the Defense Department's high-assurance Internet Protocol encryption (Haipe) architecture.

Five identical parallel processing en-gines forward IP packets in the 184x architecture. These engines handle packet encapsulation/decapsulation, as well as scheduling and load-handling. There is also a DMA and bus-control engine associated with the packet-processor block.

Also on the chip are two parallel public-key engines: one dedicated to exponentiation operations and one a general-purpose math accelerator. The math processors can support key sizes up to 4,096 bits.

SafeNet is preparing software development kits for Momentum and already offers drivers for Windows, Linux and VxWorks. SafeNet also offers its own CGX Security Platform, where designers can implement more complex functions, such as Internet Key Exchange and key-management duties.

SafeNet expects to sample all 184x family members by month's end, with production slated for the fourth quarter. Volume pricing of the chips will range from $114 to $169 each.

The 1840 and 1841 have 60-MHz system clocks and encryption clocks ranging from 65 to 240 MHz, while the 1842 has a 100-MHz system clock and an encryption clock range of 105 to 350 MHz. The chips, built in a 0.18-micron CMOS process by Samsung Electronics, are packaged in 456-lead PBGAs.

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